🤯 Chisel开发环境配置

sudo apt install openjdk-21-jdk
sudo pacman -S jdk21-openjdk # On Arch-based Distros

curl -fL https://github.com/coursier/coursier/releases/latest/download/cs-x86_64-pc-linux.gz | gzip -d > cs && chmod +x cs && ./cs setup

scala --version
# Scala code runner version: 1.5.4
# Scala version (default): 3.6.4
sbt --version
# sbt runner version: 1.10.11

.idea/
.vscode/
.metals/
.bloop/
out/
target/
generated # Chisel编译出的Verilog文件位置

ThisBuild / scalaVersion := "2.13.16"
ThisBuild / version := "1.0.0"
ThisBuild / organization := "%ORGNIZATION%" // 组织名称

val chiselVersion = "6.7.0"
val scalatestVersion = "3.2.19"

lazy val root = (project in file("."))
	.settings(
		name := "chisel-project", // 项目名称
		libraryDependencies ++= Seq(
			"org.chipsalliance" %% "chisel" % chiselVersion,
			"org.scalatest" %% "scalatest" % scalatestVersion % "test",
		),
		scalacOptions ++= Seq(
			"-language:reflectiveCalls",
			"-deprecation",
			"-feature",
			"-Xcheckinit",
			"-Ymacro-annotations",
		),
		addCompilerPlugin("org.chipsalliance" %% "chisel-plugin" % chiselVersion cross CrossVersion.full),
	)

package adder // 这里的包名和文件夹名要一致

import chisel3._
import circt.stage.ChiselStage._

class Adder extends RawModule {
	val io = IO(new Bundle {
		val a = Input(UInt(8.W))
		val b = Input(UInt(8.W))
		val sum = Output(UInt(8.W))
	})

	io.sum := io.a + io.b
}

object Main extends App {
	emitSystemVerilogFile(new Adder, args = Array("--target-dir", "generated"))
}

package adder

import chisel3._
import chisel3.simulator.EphemeralSimulator._
import org.scalatest.flatspec.AnyFlatSpec

class AdderSpec extends AnyFlatSpec {
	behavior of "Adder"
	it should "add two numbers" in {
		val testCases = Seq(
			(1.U, 2.U, 3.U),
			(0.U, 0.U, 0.U),
			(255.U, 1.U, 0.U), // overflow test
		)

		simulate(new Adder) { dut => 
			testCases.foreach { case (a, b, sum) => 
				dut.io.a.poke(a)
				dut.io.b.poke(b)
				dut.io.sum.expect(sum)
				println(s"Test case: a = $a, b = $b, sum = ${dut.io.sum.peek().litValue}")
			}
			println("All test cases passed.")
		}
	}
}

sbt runMain adder.Main # adder是包名, Main是对象名
# 或者
sbt run

sbt testOnly adder.AdderSpec
# 或者
sbt test

sudo apt install build-essential cmake
sudo pacman -S --needed base-devel cmake # On Arch-based Distros

sudo apt install verilator
sudo pacman -S verilator # On Arch-based Distros

verilator --lint-only /path/to/verilog_file.v

cmake_minimum_required(VERSION 3.10)
project(AdderTestbench)

set(CMAKE_CXX_STANDARD 17)
set(CMAKE_CXX_STANDARD_REQUIRED ON)
set(CMAKE_EXPORT_COMPILE_COMMANDS ON) # for clangd

find_package(verilator HINTS $ENV{VERILATOR_ROOT} REQUIRED)

set(VERILOG_SRC ${CMAKE_CURRENT_SOURCE_DIR}/src/rtl/Adder.sv)
set(TB_SRC ${CMAKE_CURRENT_SOURCE_DIR}/src/tb/Adder_tb.cpp)

add_executable(tb ${TB_SRC})

verilate(tb
	TRACE # 打印波形
	TOP_MODULE Adder # 指定顶层模块名称
	SOURCES ${VERILOG_SRC}
	VERILATER_ARGS -O2
)

#include "verilated.h"
#include "verilated_vcd_c.h"
#include "VAdder.h" // Verilator生成的头文件
#include <iostream>

#define MAX_SIM_TIME 1000
#define VTOP VAdder // 顶层模块名称
uint64_t sim_time = 0;

int main(int argc, char **argv, char **env) {
	Verilated::commandArgs(argc, argv);
	Verilated::traceEverOn(true); // 打开波形输出

	VTOP *top = new VTOP;
	VerilatedVcdC *tfp = new VerilatedVcdC;
	top->trace(tfp, 99); // 设置波形追踪层数
	tfp->open("waveform.vcd"); // 打开波形文件

	bool failed = false;
	while (sim_time < MAX_SIM_TIME) {
		// 向顶层模块输入信号, 例如
		// top->a = 1;
		// top->b = 1;
		top->eval(); // 评估顶层模块
		tfp->dump(sim_time); // 记录波形
		if (!/* 检查功能是否正确的条件, 比如 top->sum = 2 */) {
			std::cout << "Test failed at time " << sim_time << '\n';
			std::cout << "Expected: " << /* 预期值 */ << '\n';
			std::cout << "Got: " << /* 实际值 */ << '\n';	
			failed = true;
		}
	}

	top->final();
	tfp->close(); // 关闭波形文件
	// 清理资源
	delete top;
	delete tfp;
	// 通过返回值表明测试是否通过, 这在工具链中很有用
	return failed;
}

mkdir build && cd build
cmake ..
cmake --build . -j 0 # 0表示使用所有CPU核心进行编译
./tb # 运行仿真程序

sudo apt install gtkwave
sudo pacman -S gtkwave # On Arch-based Distros
gtkwave waveform.vcd